Hardware compilation for high performance Java processors

High performance on Java applications running on server and desktop machines requires fast execution of Java bytecodes. Such performance can be achieved by Just-In-Time (JIT) compilers, which translate the stack-based bytecodes into register-based machine code on demand. But one crucial problem in Java JIT compilation is the compilation time, which increases the total execution time of an application. So it is necessary to reduce the JIT compilation time as much as possible. In this paper we propose a front-end hardware compilation pipeline that performs the compilation of bytecodes into native machine code on-the-fly in hardware and pass the compiled code to a backend native processor for execution. The bytecodes are translated into three-address intermediate representation form, by mimicking the stack operations, before performing a series of optimizations in hardware. The optimized threeaddress codes are used for code generation and architectural register allocation and then placed in a cache for execution by the backend native processor. A micro-architecture of hardware compilation pipeline is presented.